memory bandwidth

These workloads heavily use either the floating-point units or the memory bandwidth .

这些工作负荷会占用大量的浮点单元或内存带宽。

Memory bandwidth is one of the main bottlenecks in low-end systems for ATM UNI .

内存带宽是低端系统用于ATMUNI时的主要瓶颈之一。

It can increase memory bandwidth and reduce the memory resources .

它不仅可以提高存储器带宽，而且可以减少存储器资源。

Performance Analysis of the Effective Memory Bandwidth of Delta Interconnection Networks

Delta互连网有效存贮器带宽性能分析

The system memory bandwidth is enhanced through the multi body storage architecture .

采用多体存储结构提高了系统存储带宽；

Analysis of Effective Memory Bandwidth of Prioritized Crossbar Systems

交叉开关多处理机系统有效存贮器带宽分析

Limited by memory bandwidth , high bandwidth routers often use input queued crossbar switch fabric .

由于受到存储器带宽的限制，目前宽带路由器一般采用输入缓冲的crossbar交换开关。

The memory bandwidth numbers we noticed are a little surprising considering the results in certain memory intensive applications .

记忆带宽数被的我们是稍微令人惊讶考虑某记忆强烈的申请结果。

The algorithm concerns not only the fairness of requests among cores , but also the utilization of memory bandwidth .

该算法不仅考虑了多核间的访存调度的公平性，也考虑了存储带宽的充分利用。

The results show that the whole effective memory bandwidth of multiple bus multiprocessor systems isn 't affected by the priority hierarchy .

结果表明：优先级并不影响整个系统的有效带宽性能。

The compensating measure is put forward to solve the two technological problems of sampling and memory bandwidth enhancement of high speed data acquisition systems .

对提高高速数据采集系统的采样率和存储器带宽这两大技术难题提出了补救措施。

It includes a number of optimizations that minimize memory bandwidth and therefore make it ideal for smaller , portable devices .

它包含了很多的优化，可最小化内存带宽，因而更适合于小型的便携设备。

The effective memory bandwidth performance of this system is analyzed under the assumption that the memory requests are uniformly distributed among the memory modules .

同时分析了它的有效存贮器带宽性能，获得的模型基于访存请求均匀分布于各存贮器模块。

We evaluate the effective memory bandwidth of the crossbar as a processor-memory interconnection network for multiprocessors .

本文分析了将纵横开关作为多处理机系统的处理机&存贮器互连网络时的有效存贮器带宽。

The course of their work in graphics , Z buffer , frame buffer and texture buffer memory bandwidth will be substantially occupied resources .

在显卡工作过程中，Z缓冲器、帧缓冲器和纹理缓冲器都会大幅占用显存带宽资源。

Each time data traverses the user-kernel boundary , it must be copied , which consumes CPU cycles and memory bandwidth .

数据每遍历用户内核一次，就要被拷贝一次，这会消耗CPU周期和内存带宽。

Associated with the characteristics of FGS algorithm , it chooses the most suitable data type for storage of FGS algorithm to save much external memory bandwidth .

并结合FGS算法的特点，选择FGS算法中最适当的数据存储类型，节省了大量的外存带宽。

In the field of signal processing , high efficiency network , and high definition audio / video , memory bandwidth has increasingly become a bottleneck , especially in multi-core SoC designs .

在信号处理、高性能网络设备和高清音视频等领域，尤其对于多核SoC设计，存储器带宽越来越成为限制系统性能的瓶颈。

High-performance microprocessor architectures have involved into many-core ones due to the demand for large-scale data-level parallel applications with respect to scalability , computational power and memory bandwidth .

大规模数据并行应用对可扩展性、计算能力和存储带宽的迫切需求促使高性能微处理器正在向众核体系结构演变。

As is used for data-intensive applications , heterogeneous multi-core DSPs need higher memory bandwidth , more flexible memory structures and more powerful data-paths on-chip than normal DSPs .

异构多核DSP在处理数据流密集型应用时，相比单核DSP需要更大的存储带宽和更灵活的存储结构，对片上存储系统和数据通路具有更高的性能要求。

On the other hand , the recent rapidly developing General Purpose computing on GPU ( GPGPU ) technology makes it possible to manipulate the GPU with strong computational capability , high memory bandwidth and relatively low cost for general usage .

另一方面，近年来通用图形计算技术（GPGPU）的高速发展使得利用计算能力强、存储带宽高而相对开销较小的图形处理器（GPU）实现通用运算成为可能。

Now the GPU already has good programmability . It has evolved into a highly parallel , multi-core , multi-threaded processor . Comparing with CPUs , GPUs have outstanding advantage in computing power and memory bandwidth .

目前的GPU已经具备了很好的可编程能力，并发展成为一种高并行、多核、多线程的处理器，其计算功率和存储器带宽相较于CPU有着杰出的优势。

In order to exerting the advantages of memory bandwidth of GPU architectures , this paper proposes memory optimization methods by means of polyhedral model . Polyhedral representation of a source program is built to optimize and allocate GPU memory system .

为了充分发挥GPU体系结构在存储带宽方面的优势，本文提出了基于多面体模型的存储优化方法。

The numerical experiment results show that the speed is increased by more than 10 ~ 2 times . In addition , we optimize the storage of texture in the algorithm , which saves video memory bandwidth , and is more suitable for reconstruction of multi-scan mode .

同时算法中优化了纹理存储方式，节约了显存带宽，更适合多次偏置扫描模式的重建，算法运行速度比CPU上的运行速度快了两个数量级。

Then , we design and implement a Shared by Heterogeneity Processor L2 Cache sub-system to exploit the extra parallelism and locality in stream application , and improve the off-chip memory bandwidth . These lead to a more completed parallel hierarchy stream memory system .

针对流应用中各种可用的并行性和局域性，我们设计并实现了由异构处理器共享的二级缓存子系统，并对片外存储层次进行改进，完善了原有的存储层次结构。

Modern graphics application systems have to render many geometric datasets , thus facing the problems of memory and bandwidth .

现代图形应用系统需要绘制大量的几何体，这给绘制硬件带来内存、带宽等问题。

Computer systems and network systems must allocate enough resources such as CPU , I / O , memory and bandwidth to guarantee the QoS .

为了保证QoS，计算机系统和网络系统必须分配足够的CPU、I/O、内存和网络带宽资源。

Compared with other public-key cryptosystems , ECC has shorter key , this means higher speed , fewer memory and bandwidth .

相比其它公钥密码体制，ECC有更短的密钥，这意味着更快的运算速度，更少的存储空间和带宽。

Single-path delay feedback pipeline can improve the processing speed and lower the restriction of the external memory data bandwidth with favorable chip pins .

单路径延迟反馈流水结构的设计提高了计算速度，降低了对于外部存储器数据带宽的限制，有效控制了芯片引脚。

The result shows that this routing protocol has the obvious advantages of fast networking , sensitive topological reaction and low overhead on CPU 、 memory and bandwidth .

测试结果表明，本路由协议具有组网迅速、拓扑反应灵敏、对CPU、内存和带宽开销较小等显著优点。